/*
 *	ApOS (Another Project software for s3c2410)
 *	
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License version 2 as
 *	published by the Free Software Foundation.
 *			
 *
 */
#ifndef _CLOCK_H
#define _CLOK_H

#define MDIV_202MHz 0xa1
#define PDIV_202MHz 0x03
#define SDIV_202MHz 0x01

#define MDIV_170MHz 0x4d
#define PDIV_170MHz 0x01
#define SDIV_170MHz 0x01

#define MDIV_90MHz 0x70
#define PDIV_90MHz 0x02
#define SDIV_90MHz 0x02

#define MDIV_50MHz 0xa1
#define PDIV_50MHz 0x3
#define SDIV_50MHz 0x3

#define vMPLLCON_202MHz		((MDIV_202MHz << 12)|(PDIV_202MHz<<4)|(SDIV_202MHz)) 
#define vMPLLCON_170MHz		((MDIV_170MHz << 12)|(PDIV_170MHz<<4)|(SDIV_170MHz))
#define vMPLLCON_90MHz		((MDIV_90MHz << 12)|(PDIV_90MHz<<4)|(SDIV_90MHz))
#define vMPLLCON_50MHz		((MDIV_50MHz << 12)|(PDIV_50MHz<<4)|(SDIV_50MHz))

#define FCLK_202MHz	202800000
#define FCLK_170MHz	170000000
#define FCLK_90MHz	90000000
#define FCLK_50MHz	50700000


#endif


